The present invention relates to a display apparatus for performing pixel density conversion processing, such as enlargement, reduction, and rotation, on an original image and for displaying a resultant image, or to an image processing apparatus, and, more particularly, to a processing apparatus for performing a high-speed filtering operation, such as data interpolation, which involves pixel density conversion processing, and to a memory having an arithmetic function for use in the high-speed filtering operation.
A conventional display apparatus for performing enlargement, reduction, and rotation on an image is used in texture mapping apparatuses, such as disclosed in Japanese Non-examined Patent Publication Nos. Hei 5-298455 and Hei 5-307610. In these publications, methods are disclosed in which, when the coordinate value of an original image corresponding to its destination does not match the center of a pixel of the original image, the value of the pixel of a specified coordinate is estimated by interpolation of pixels around the specified pixel. For enlargement of a binary character image, Japanese Non-examined Patent Publication No. Sho 59-6626 discloses a method of obtaining destination pixels enlarged from plural pixels of an original image. In addition, for image differentiation and integration in image processing, a method is well known in which a product-sum operation is performed by weighting the surrounding eight pixels.
The conventional processing apparatus, such as mentioned above, for reading plural pixels from an original image for arithmetic operations has plural memory devices and arithmetic units arranged in parallel to perform parallel processing for high-speed processing.
However, when arranging plural memory devices and reading data at high speeds from an original image for processing, the above-mentioned prior-art technologies present a problem in that the number of signal lines between the processor for performing that processing and the plural memory devices is significantly increased. For example, if one pixel consists of 24 bits (red, green, and blue consisting of eight bits each) and an arithmetic operation is performed from an original image consisting of four pixels, data lines for 96 bits are required. The data reading performance of a memory device itself, if the same is an ordinary random access memory, is currently limited to 150 ns in a random access operation. In order to achieve a target performance, this access speed must be further increased by parallel processing, which in turn increases the number of signal lines still further. This inevitably increases the equipment scale as well as the equipment cost because the individual performance (operating frequency) needs to be increased.